S. Lee, J. Lee, H. Lee and S. Kang, "VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2025.3593691.

J. Joung, S. Lee, J. Park, J. Kim, L. Jung and S. Kang, "CLAPS: A Graph Clustering Based Approach for Partial Scan Design," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2025.3576314.

D. Han, D. Won, S. Kim and S. Kang, "TSV Built-In Self-Repair Architecture for Lifespan Reliability Enhancement of HBM," in IEEE Transactions on Reliability, doi: 10.1109/TR.2024.3434631.

H. Lee, J. Lee and S. Kang, "An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 5, pp. 1452-1456, May 2025, doi: 10.1109/TVLSI.2024.3504539.

J. Lee, H. Lee, S. Lee and S. Kang, "A New ISA for High-Speed and Area-Efficient ALPG," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 7, pp. 3358-3362, July 2024, doi: 10.1109/TCSII.2024.3364057.